I’m a Ph.D student in MIT CSAIL‘s Networks and Mobile Systems group, advised by Hari Balakrishnan and Devavrat Shah. I received a B.Sc. in Computer Science from Tel-Aviv University in 2003, after which I worked for 7 years in communication systems R&D and HPC algorithm development in an army technological unit.
My current research focuses on enabling faster and more complex datacenter applications, by designing datacenter networks and operating system components that provide predictable, low-latency communication between endpoints. Fastpass aims for high utilization with zero queueing: a logically centralized arbiter controls and orchestrates all network transfers.
Other research deals with rateless error correcting codes for wireless networks: Spinal Codes (w/source code) are efficient, high-performance error correction codes, especially suited for analog channels.
- J. Perry, A. Ousterhout, H. Balakrishnan, D, Shah, H. Fugal, Fastpass: A Centralized “Zero-Queue” Datacenter Network, SIGCOMM 2014.
- J. Perry, P. Iannucci, K. Fleming, H. Balakrishnan, D, Shah, Spinal Codes, SIGCOMM 2012.
- J. Perry, H. Balakrishnan, D. Shah, Rateless Spinal Codes, HotNets 2011.
- P. Iannucci, J. Perry, H. Balakrishnan, D. Shah, No Symbol Left Behind: A Link-Layer Protocol for Rateless Codes, MobiCom 2012.
- D. Shah, J. Perry, P. Iannucci, H. Balakrishnan, De-randomizing Shannon: The Design and Analysis of a Capacity-Achieving Rateless Code, Manuscript in preparation/submission.
- P. Iannucci, K. Fleming, J. Perry, H. Balakrishnan, D. Shah, A Hardware Spinal Decoder, ANCS 2012.